1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, and particularly to a method for manufacturing MOS transistors used in DRAMs, logic circuits, etc.
2. Description of the Background Art
FIGS. 47 to 54 are sectional views showing a conventional method for manufacturing CMOS transistors (CMOSFETs). The CMOS transistor manufacturing method will now be described referring to these diagrams.
First, as shown in FIG. 47, element isolation regions 61 are selectively formed in the upper part of a silicon substrate 60. Next, a P well region 83 and an N well region 84 (both of which include a channel region) are formed by ion implantation etc. in the NMOS region 81 and the PMOS region 82 which are isolated by the element isolation regions 61. A silicon oxide film 62 and a polysilicon layer 63 are then sequentially deposited on the entire surface of the silicon substrate 60.
Next, as shown in FIG. 48, resist 64 is formed on the polysilicon layer 63 and patterned by photolithography.
Next, as shown in FIG. 49, the polysilicon layer 63 and the silicon oxide film 62 are etched using the patterned resist 64 as a mask to obtain gate electrodes (interconnections) 65 and gate oxide films 79.
Subsequently, as shown in FIG. 50, resist 66 is formed on the entire surface and patterned so that it remains only in the PMOS region 82, and N-type impurity ions 67 are implanted relatively shallowly from the surface of the silicon substrate 60 by using the patterned resist 66 and the gate electrode 65 in the NMOS region 81 as masks to obtain N-type diffusion regions 68 (68a and 68b).
Next, as shown in FIG. 51 a silicon oxide film is deposited on the entire surface and etched back to form side walls 69 (69a and 69b) of silicon oxide film on the sides of the gate electrodes 65.
Subsequently, as shown in FIG. 52, resist 70 is formed on the entire surface and patterned so that the resist 70 remains only in the NMOS region 81, and P-type impurity ions 71 are implanted relatively deep from the surface of the silicon substrate 60 by using the patterned resist 70 and the gate electrode 65 and side walls 69 in the PMOS region 82 as masks, so as to obtain P-type diffusion regions 72 (72a and 72b). The P-type diffusion regions 72 are formed deeper from the surface of the silicon substrate 60 than the N-type diffusion regions 68.
Next, as shown in FIG. 53, resist 73 is formed all over the surface and patterned so that the resist 73 remains only in the PMOS region 82. N-type impurity ions 74 are then implanted relatively deep from the surface of the silicon substrate 60 by using the patterned resist 73 and the gate electrode 65 and side walls 69 in the NMOS region 81 as masks, thus forming N-type diffusion regions 75 (75a and 75b) which are merged with the previously formed N-type diffusion regions 68 to form main source/drain regions.
The N-type diffusion regions 75 serve as the source/drain regions of the NMOS transistor and the N-type diffusion regions 75 under the side walls 69 serve as extension regions 75ae and 75be which are shallower from the surface of the silicon substrate 60.
Next, as shown in FIG. 54, an interlayer insulating film 76 of silicon oxide film is deposited all over the surface. A thermal process applied in this process causes the N-type diffusion regions 75 and the P-type diffusion regions 72 to further diffuse to form N-type diffusion regions 77 (77a and 77b) and P-type diffusion regions 78 (78a and 78b). Accordingly, the formation depth of the extension regions 77ae and 77be in the N-type diffusion regions 77 is deeper than that of the extension regions 75ae and 75be. Also, the formation depth of the extension regions 77ae and 77be is made deeper than that of the N-type diffusion regions 68 by thermal processes performed between the formation of the N-type diffusion regions 68 and the formation of the interlayer insulating film 76.
The semiconductor device having the CMOS transistors is then completed through existing processes such as interconnecting etc.
Important factors to enhance the driving capability and operating speed of MOSFETs and improve the short-channel characteristic include the reduction of gate dimension (gate length), reduction of source/drain resistance, and formation of shallower PN junctions.
Among these factors, obtaining shallower PN junctions, or forming shallower extension regions, can be achieved by reducing the amount of thermal treatments which are performed after the formation of the extension regions and contribute to the impurity diffusion. However, in the conventional CMOS transistor manufacturing method as shown in FIGS. 47 to 54, thermal processes such as annealing are performed, after the formation of the N-type diffusion regions 68 as extension regions, to form the side walls 69 and to activate the N-type diffusion regions 75 as the main source/drain regions; the thermal processes diffuse the extension regions further deeper, which makes it difficult to form shallower PN junctions.
According to a first aspect of the present invention, a semiconductor device manufacturing method comprises the steps of: (a) forming first and second main source/drain regions of a first conductivity type in a surface of a semiconductor substrate and a temporary gate electrode portion on the semiconductor substrate between the first and second main source/drain regions; (b) forming first and second auxiliary side walls on sides of the temporary gate electrode portion; (c) removing the temporary gate electrode portion to obtain an opening w hose sides are defined by the first and second auxiliary side walls; (d) forming first and second extension-forming side walls adjacent respectively to the first and second auxiliary side walls in the opening, the first and second extension-forming side walls containing a first extension-forming impurity of the first conductivity type; (e) after the step (d), sequentially forming a first real gate insulating film and a first real gate electrode in the opening to obtain a first real gate electrode portion; and (f) forming first and second extension regions of the first conductivity type adjacent respectively to the first and second main source/drain regions through a first diffusion process where the first extension-forming impurity in the first and second extension-forming side walls serves as a diffusion source, wherein the first real gate insulating film, the first real gate electrode, the first and second main source/drain regions and the first and second extension regions define an insulated-gate, first transistor of the first conductivity type.
Preferably, according to a second aspect of the invention, in the semiconductor device manufacturing method, the step (f) includes a step of forming an interlayer insulating film all over the surface of the semiconductor substrate including the first transistor, and the first diffusion process includes a diffusion process utilizing a thermal process carried out during formation of the interlayer insulating film.
Preferably, according to a third aspect of the invention, in the semiconductor device manufacturing method, the first and second extension-forming side walls include side walls further containing a pocket-forming impurity of a second conductivity type, and the step (f) comprises a step of further forming first and second pocket regions adjacent to the first and second main source/drain regions through a second diffusion process where the pocket-forming impurity serves as a diffusion source.
Preferably, according to a fourth aspect of the invention, in the semiconductor device manufacturing method, the pocket-forming impurity has a larger diffusion coefficient than the first extension-forming impurity.
Preferably, according to a fifth aspect of the invention, in the semiconductor device manufacturing method, the step (f) includes a step of forming an interlayer insulating film all over the surface of the semiconductor substrate including the first transistor, and the first and second diffusion processes include diffusion processes performed at the same time by utilizing a thermal process carried out during formation of the interlayer insulating film.
Preferably, according to a sixth aspect of the invention, in the semiconductor device manufacturing method, the first real gate electrode is formed using a gate electrode material including a gate electrode material of the first conductivity type.
Preferably, according to a seventh aspect of the invention, the semiconductor device manufacturing method further comprises the step of: (g) performing an impurity introducing process in which an impurity of a second conductivity type is introduced into a predetermined semiconductor region at least including the region in the surface of the semiconductor substrate under the region where the first real gate electrode portion is to be formed.
Preferably, according to an eighth aspect of the invention, in the semiconductor device manufacturing method, the step (g) includes a step performed after the step (c), and the impurity introducing process includes an ion implantation process of implanting impurity ions of the second conductivity type through the opening.
Preferably, according to a ninth aspect of the invention, in the semiconductor device manufacturing method, the semiconductor substrate includes first and second formation regions and the temporary gate electrode portion is composed of a stacked structure of a temporary gate insulating film and a temporary gate electrode. The step (a) includes the steps of: (a-1) forming the temporary gate electrode portion on the first formation region and forming a second real gate electrode portion having a stacked structure of a second real gate insulating film and a second real gate electrode on the second formation region; and (a-2) introducing a first source/drain forming impurity of the first conductivity type by using the temporary gate electrode portion as a mask to form the first and second main source/drain regions, and the step (b) includes a step of further forming third and fourth extension-forming side walls on sides of the second real gate electrode, the third and fourth extension-forming side walls contain a second extension-forming impurity of a second conductivity type. The manufacturing method further comprises the step of (h) after the step (b), introducing a second source/drain forming impurity of the second conductivity type by using the second real gate electrode and the third and fourth extension-forming side walls as masks to form third and fourth main source/drain regions of the second conductivity type in the surface of the second formation region in areas separated by the region under the second real gate electrode and the third and fourth extension-forming side walls, and the step (f) includes a step of further forming third and fourth extension regions of the second conductivity type adjacent respectively to the third and fourth main source/drain regions through a third diffusion process where the second extension-forming impurity in the third and fourth extension-forming side walls serves as a diffusion source. The second real gate insulating film, the second real gate electrode, the third and fourth main source/drain regions and the third and fourth extension regions define an insulated-gate, second transistor of the second conductivity type.
Preferably, according to a tenth aspect of the invention, in the semiconductor device manufacturing method, the first and second auxiliary side walls include side walls containing the second extension-forming impurity, and the step (b) includes a step of simultaneously forming the first and second auxiliary side walls and the third and fourth extension-forming side walls.
Preferably, according to an eleventh aspect of the invention, in the semiconductor device manufacturing method, the first real gate electrode is formed by using a gate electrode material including a gate electrode material of the first conductivity type, and the second real gate electrode is formed by using a gate electrode material including a gate electrode material of the second conductivity type.
Preferably, according to a twelfth aspect of the invention, in the semiconductor device manufacturing method, the temporary gate electrode is formed by using a gate electrode material including a gate electrode material of the second conductivity type, and the step (a-1) includes a step of simultaneously forming the temporary gate electrode and the second real gate electrode.
A thirteenth aspect of the present invention is directed to a semiconductor device having an insulated-gate transistor of a first conductivity type. The semiconductor device comprises: a semiconductor substrate having a predetermined semiconductor region of a second conductivity type in its surface; a gate insulating film selectively formed on the predetermined semiconductor region, the surface of the predetermined semiconductor region under the gate insulating film being defined as a channel region; a gate electrode formed on the gate insulating film; first and second extension-forming side walls formed on sides of the gate electrode and containing an extension-forming impurity of the first conductivity type: first and second auxiliary side walls adjacent respectively to the first and second extension-forming side walls: and first and second source/drain regions separated by the channel region in the surface of the predetermined semiconductor region, wherein the gate insulating film, the gate electrode and the first and second source/drain regions define the transistor, and the source/drain regions include first and second extension regions which are shallower than other regions and formed under the first and second extension-forming side walls.
Preferably, according to a fourteenth aspect of the invention, in the semiconductor device, the first and second extension-forming side walls further include a pocket-forming impurity of the second conductivity type, and the source/drain regions further include first and second pocket regions of the second conductivity type formed under the first and second extension-forming side walls.
Preferably, according to a fifteenth aspect of the invention, in the semiconductor device, the gate electrode is formed by using a gate electrode material including a gate electrode material of the first conductivity type.
As stated above, according to the semiconductor device manufacturing method of the first aspect of the invention, in the step (f) performed after formation of the first and second main source/drain regions, the first and second extension regions of the first conductivity type respectively adjacent to the first and second main source/drain regions are formed by the first diffusion process where the first extension-forming impurity in the first and second extension-forming side walls serves as the diffusion source.
Accordingly, a thermal process performed during formation of the first and second main source/drain regions does not affect the first and second extension regions at all. Thus removing the effect of the thermal process performed during formation of the first and second main source/drain regions allows the first and second extension regions to have a shallow formation depth.
Further, forming the first and second extension-forming side walls adjacent to the previously formed first and second auxiliary side walls allows the extension regions to be precisely positioned next to the main source/drain regions during the first diffusion process.
In the semiconductor device manufacturing method of the second aspect, the first diffusion process in the step (f) utilizes a thermal process performed during formation of an interlayer insulating film. Accordingly the extension regions can be formed without the need for adding a separate process for forming the extension regions.
In the semiconductor device manufacturing method of the third aspect, the step (f) further forms first and second pocket regions through the second diffusion process where the pocket-forming impurity serves as the diffusion source. Accordingly it is possible to manufacture the insulated-gate, first transistor having the pocket regions as well as the extension regions in areas adjacent to the main source/drain regions.
In the semiconductor device manufacturing method of the fourth aspect, the pocket-forming impurity has a larger diffusion coefficient than the first extension-forming impurity. The difference in diffusion coefficient causes the first and second extension regions to form in relatively shallow regions from the semiconductor substrate surface and the first and second pocket regions to form in relatively deep regions from the semiconductor substrate surface, whereby the first and second extension regions and the first and second pocket regions are certainly formed in separate areas.
In the semiconductor device manufacturing method of the fifth aspect, the first and second diffusion processes in the step (f) are carried out at the same time by utilizing a thermal process performed during formation of the interlayer insulating film. The first and second extension regions and the first and second pocket regions can thus be formed at the same time without the need for adding a separate process for forming the extension regions and the pocket regions.
In the semiconductor device manufacturing method of the sixth aspect, the gate electrode material used to form the first real gate electrode includes a gate electrode material of the first conductivity type, so that the first real gate electrode can be adapted to the work function of the first transistor of the first conductivity type.
The step (g) in the semiconductor device manufacturing method of the seventh aspect provides a first transistor in which the region in the surface of the semiconductor substrate under the region where the first real gate electrode portion is formed serves as a channel region of the second conductivity type.
In the semiconductor device manufacturing method of the eighth aspect, the step (g) includes an ion implantation process of implanting impurity ions of the second conductivity type through the opening, which allows the second-conductivity-type channel region to be formed in precise position under the first real gate electrode formed in the opening in the step (e).
Furthermore, since the channel region is formed after the first and second main source/drain regions have been formed, it is possible to remove the effect of impurity redistribution caused by a thermal process performed during formation of the main source/drain regions.
In the semiconductor device manufacturing method of the ninth aspect, the step (f) further forms third and fourth extension regions of the second conductivity type through the third diffusion process where the second extension-forming impurity in the third and fourth extension-forming side walls is used as the diffusion source.
Accordingly, a thermal process performed during formation of the third and fourth main source/drain regions does not affect the third and fourth extension regions at all. Since the effect of the thermal processing during formation of the third and fourth main source/drain regions is thus removed, the third and fourth extension regions can be formed to a shallow formation depth.
Moreover, the temporary gate electrode portion and the second real gate electrode portion both have a stacked structure composed of a gate insulating film (the temporary gate insulating film and the second real gate insulating film) and a gate electrode (the temporary gate electrode and the second real gate electrode). Hence, when the temporary gate insulating film and the temporary gate electrode are formed with the same materials respectively as the second real gate insulating film and the second real gate electrode, the temporary gate electrode portion and the second real gate electrode portion can be formed at the same time so as to simplify the manufacturing process.
In the semiconductor device manufacturing method of the tenth aspect, the first and second auxiliary side walls and the third and fourth extension-forming side walls both containing the second extension-forming impurity can be formed at the same time so as to simplify the manufacturing process.
In the semiconductor device manufacturing method of the eleventh aspect, the gate electrode materials used to form the first and second real gate electrodes respectively include first- and second-conductivity-type gate electrode materials, so that the first and second real gate electrodes can be adapted to the work functions of the first and second transistors of the first and second conductivity types, respectively.
In the semiconductor device manufacturing method of the twelfth aspect, the temporary gate electrode and the second real gate electrode both made of a second-conductivity-type gate electrode material can be simultaneously formed in the step (a-1), so that the manufacturing process can be simplified.
In the semiconductor device of the thirteenth aspect, the first and second extension regions formed shallower than other regions under the first and second extension-forming side walls can be obtained by a first diffusion process where the extension-forming impurity in the first and second extension-forming side walls serves as the diffusion source.
Accordingly, for example, the transistor of the thirteenth aspect can be obtained by: implanting an impurity using a temporary gate electrode portion as a mask to form the first and second main source/drain regions; forming the first and second auxiliary side walls adjacent to the temporary gate electrode portion; removing the temporary gate electrode portion to form an opening; forming in the opening the first and second extension-forming side walls adjacent to the first and second auxiliary side walls; forming a real gate electrode portion (the gate insulating film and gate electrode) in the remaining opening; and performing the first diffusion process, where the extension regions can be precisely positioned next to the main source/drain regions.
Furthermore, in the manufacturing process shown above, a thermal process performed during formation of the first and second main source/drain regions does not at all affect the first and second extension regions: removing the effect of the thermal process performed during the formation of the first and second main source/drain regions enables the first and second extension regions to have shallow junction depth.
In the semiconductor device of the fourteenth aspect, the second-conductivity-type first and second pocket regions formed under the first and second extension-forming side walls can be obtained through a second diffusion process where the pocket-forming impurity in the first and second extension-forming side walls is used as the diffusion source.
Thus, precisely positioned first and second pocket regions adjacent to the first and second main source/drain regions can be obtained by performing the second diffusion process after the formation of the first and second main source/drain regions.
In the semiconductor device of the fifteenth aspect, the gate electrode material for forming the gate electrode includes a gate electrode material of the first conductivity type, so that the first real gate electrode can be adapted to the work function of the first transistor of the first conductivity type.
The present invention has been made to solve the aforementioned problem, and an object of the present invention is to provide a semiconductor device manufacturing method capable of forming shallow extension regions in insulated-gate transistors.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.